An integrated circuit (IC) typically includes numerous connections between electrical components. These connections are often designed with the assistance of an electronic design automation (EDA) tool. The EDA tool typically includes software instructions operating on an engineering workstation to provide visualization of the IC design. A design engineer manipulates modular design cells from a cell library to build up a design database. An autorouter within the EDA tool determines the connection paths between the design cells. When the design layout is complete, the layout data are used in a pattern generation (PG) step that generates pattern data suitable to produce a set of pattern masks used in photolithographic steps of an IC manufacturing process.
Before the PG step, the designer may perform a gate-level simulation of the IC design and estimate the power consumption of the IC from simulated activity on the IC. If the estimate exceeds a design objective, the designer may revise the design database to reduce the power consumption locally or globally as needed to meet the relevant design objective. The designer may again perform a gate-level simulation to determine if the revised design meets the design objective. This revision cycle consumes significant time, as the gate-level simulation of even a moderately complex IC design may require significant time and computational resources.